基于迭代單元的恢復(fù)余數(shù)開方器

基本算法

該開方器的算法與“手算”（以前并不知道開方還有這種手算的方法）算法相似，使用迭代解決，文字描述如下

1. 將0為余數(shù)的初值a，0作為結(jié)果初值b
2. 將被開方數(shù)前兩位{I(2m + 1),I(2m)}取出，與01比較大小。若前兩位大，則{I(2m + 1),I(2m)} - 01為輸出余數(shù)（a(m)），輸出結(jié)果1(b(m))，否則{I(2m + 1),I(2m)}為輸出余數(shù)（a(m)），輸出結(jié)果0（b(m)）
3. 將被開方數(shù)的從高位數(shù)第3,4位{I(2m - 1),I(2m - 2)}取出，比較{a(m),I(2m - 1),I(2m - 2)}和{b(m),2'b01}的大小，若前一項大，則輸出余數(shù)a(m - 1)為前一項減后一項，輸出結(jié)果b(m - 1)為{b(m),1};否則，輸出余數(shù)為前一項（直接輸出），輸出結(jié)果b(m - 1)為{b(m),0}
4. ...
5. 直到計算完被開方數(shù)結(jié)束

迭代單元

算法

迭代單元的算法比較簡單，描述如下：

1. 組合輸入余數(shù)和當(dāng)前開方數(shù)的兩位{b,I(i),I(i - 1)}，組合輸入結(jié)果和01為{a,2'b01}
2. 比較大小，若組合余數(shù)大則輸出余數(shù)為組合余數(shù)減去組合結(jié)果，輸出結(jié)果{a,1}；否則余數(shù)輸出組合余數(shù)，結(jié)果輸出{a,0}

RTL代碼

module square_cell #(
    parameter WIDTH = 4,
    parameter STEP = 0
)(
    input clk,    // Clock
    input rst_n,  // Asynchronous reset active low

    input [2 * WIDTH - 1:0]radicand,
    input [WIDTH - 1:0]last_dout,
    input [2 * WIDTH - 1:0]remainder_din,

    output reg [WIDTH - 1:0]this_dout,
    output reg [2 * WIDTH - 1:0]remainder_dout
);

wire [2 * WIDTH - 1:0]target_data = {remainder_din[2 * WIDTH - 3:0],radicand[2 * STEP +:2]};
wire [2 * WIDTH - 1:0]try_data = {last_dout,2'b01};

always @(posedge clk or negedge rst_n) begin
    if(~rst_n) begin
        {this_dout,remainder_dout} <= 'b0;
    end else begin
        if(target_data >= try_data) begin
            this_dout <= {last_dout[WIDTH - 2:0],1'b1};
            remainder_dout <= target_data - try_data;
        end else begin
            this_dout <= {last_dout[WIDTH - 2:0],1'b0};
            remainder_dout <= target_data;
        end
    end
end
endmodule

頂層與Testbench

頂層單元

module square_extractor #(
    parameter WIDTH = 4
)(
    input clk,    // Clock
    input rst_n,  // Asynchronous reset active low

    input [2 * WIDTH - 1:0]radicand,

    output [WIDTH - 1:0]dout,
    output [2 * WIDTH - 1:0]remainder
);

genvar i;
generate
    for (i = WIDTH - 1; i >= 0; i = i - 1) begin:square
        wire [2 * WIDTH - 1:0]remainder_dout,remainder_din;
        wire [WIDTH - 1:0]this_dout,last_dout;
        if(i == WIDTH - 1) begin
            assign remainder_din = 'b0;
            assign last_dout = 'b0;
        end else begin
            assign remainder_din = square[i + 1].remainder_dout;
            assign last_dout = square[i + 1].this_dout;
        end
        square_cell #(
            .WIDTH(WIDTH),
            .STEP(i)
        ) u_square_cell (
            .clk(clk),    // Clock
            .rst_n(rst_n),  // Asynchronous reset active low

            .radicand(radicand),
            .last_dout(last_dout),
            .remainder_din(remainder_din),

            .this_dout(this_dout),
            .remainder_dout(remainder_dout)
        );
    end
endgenerate

assign dout = square[0].this_dout;
assign remainder = square[0].remainder_dout;

endmodule

TestBench

Testbench輸入隨機(jī)的輸入后，等待完成，完成后取結(jié)果和余數(shù)看是否能恢復(fù)出正確的輸入

module tb_square (
);

parameter WIDTH = 4;

logic clk;    // Clock
logic rst_n;  // Asynchronous reset active low

logic [2 * WIDTH - 1:0]radicand;

logic [WIDTH - 1:0]dout;
logic [2 * WIDTH - 1:0]remainder;

square_extractor #(
    .WIDTH(WIDTH)
) dut (
    .clk(clk),    // Clock
    .rst_n(rst_n),  // Asynchronous reset active low

    .radicand(radicand),

    .dout(dout),
    .remainder(remainder)
);

initial begin
    clk = 0;
    forever begin
        #50 clk = ~clk;
    end
end

initial begin
    rst_n = 1'b1;
    #5 rst_n = 1'b0;
    #10 rst_n = 1'b1;
end

logic [2 * WIDTH - 1:0]act;
logic [2 * WIDTH - 1:0]dout_ex;
initial begin
    radicand = 'b0;
    forever begin
        @(negedge clk);
        radicand = (2 * WIDTH)'($urandom_range(0,2 ** (2 * WIDTH)));
        repeat(4 * WIDTH) begin
            @(negedge clk);
        end
        dout_ex = '{dout};
        act = dout_ex * dout_ex + remainder;
        if(act != radicand) begin
            $stop;
        end
    end
end

endmodule