// ======================================================
// Project name : router
//
// Author : logan
// Filename: router_interface.sv
// Created: 2022-07-03
// Last modified: 2022-07-03
// Abstracted
//
//
//
// ====================================================
`ifndef ROUTER_INTERFACE_SV // 防止代碼沖突
`define ROUTER_INTERFACE_SV
interface router_interface(input clock);
logic reset_n;
logic [15:0] din;
logic [15:0] frame_n;
logic [15:0] valid_n;
logic [15:0] dout;
logic [15:0] valido_n;
logic [15:0] busy_n;
logic [15:0] frameo_n;
clocking cb @(posedge clock);
output din;
output frame_n;
output valid_n;
input dout;
input valido_n;
input busy_n;
input frameo_n;
endclocking :cb
modport TB(clocking cb , output reset_n);
endinterface:router_interface
`endif // ROUTER_INTERFA
tb_top.sv
`ifndef TB_TOP_SV
`define TB_TOP_SV
`include "./tb/tb_include.svh"
module tb_top;
bit clk;
// instance interface
router_inferace u_router_interface(.clock(clk));
// instance dut
router u_router(
.reset_n (u_router_interface.reset_n),
.clock (clk),
.frame_n (u_router_interface.frame_n),
.valid_n (u_router_interface.valid_n),
.din (u_router_interface.din),
.dout (u_router_interface.dout),
.busy_n (u_router_interface.busy_n),
.valido_n (u_router_interface.valido_n),
.frameo_n (u_router_interface.frameo_n)
);
// instance tc
interface_reset_test u_interface_reset_test(u_router_interface);
// clk 4ns
initial begin
clk = 0;
forever #2 clk = ~clk;
end
endmodule:tb_top
`endif// TB_TOP_SV